1. Field of the Invention
The invention relates to the protection of integrated circuits from electrostatic discharge (ESD), and more particularly to the protection of high voltage NMOS transistors by parasitic silicon controlled rectifiers (SCR) which carry equal currents.
2. Description of the Related Art
The protection of integrated circuits from electrostatic discharge (ESD) is a subject which has received a lot of attention from circuit designers because of the serious damage that ESD can wreak as device dimensions are reduced. Workers in the field and inventors have proposed many solutions, many trying to solve the problem of protecting sub-micron devices while still allowing them to function unencumbered and without undue, or zero, increase of silicon real estate. The main thrust of ESD protection for MOS devices is focused on the use of parasitic npn and pnp bipolar transistors which together form a lateral silicon controlled rectifier (SCR). Unwanted as this SCR normally is, it can safely discharge dangerous ESD voltages as long as its trigger voltage is low enough to protect those MOS devices of which it is a part.
The following publications discuss lateral SCR structures for ESD protection circuits:
xe2x80x9cLateral SCR Devices with Low-Voltage High-Current Triggering Characteristics for Output ESD Protection in Submicron CMOS Technology,xe2x80x9d Ker, IEEE Transactions On Electron Devices, Vol. 45, No. 4, April 1999, pp. 849-860.
xe2x80x9cGrounded-Gate nMos Transistor Behavior Under CDM ESD Stress Conditions,xe2x80x9d Verhaege et al., IEEE Transactions On Electron Devices, Vol. 44, No. 11, November 1997, pp. 1972-1980.
xe2x80x9cDesign Methodology and Optimization of Gate-Driven NMOS ESD Protection Circuits in Submicron CMOS Processes,xe2x80x9d Chen et al., IEEE Transactions On Electron Devices, Vol. 45, No. 12, December 1998, pp. 2448-2456.
xe2x80x9cThe State of the Art of Electrostatic Discharge Protection: Physics, Technology, Circuits, Design, Simulation, and Scaling,xe2x80x9d Voldman, IEEE Journal of Solid-State Circuits, Vol. 34, No. 9, September 1999, pp. 1272-1282.
xe2x80x9cThe Mirrored Lateral SCR (MILSCR) as an ESD Protection Structure: Design and Optimization Using 2-D Device Simulation,xe2x80x9d Delage et al., IEEE Journal of Solid-State Circuits, Vol. 34, No. 9, September 1999, pp. 1283-1289.
FIG. 1 is a cross-sectional schematic of a high voltage protection device layout of the prior art and FIG. 2 is the equivalent circuit. FIG. 1 shows a semiconductor wafer 100 with a p-substrate 102 having two n-wells 104, and 105, where n-wells 104 and 105 are NMOS drains. Implanted in n-well 104 are n+ diffusions 106, 108, and p+ diffusion 110 (all connected together via connection 122). Implanted into p-substrate 102 are p+ diffusion 112 and n+ diffusion 114 to one side of n-well 106, and n+ diffusion 116 to the other side of n-well 104. Diffusions 112, 114, and 116 are all connected to a reference potential 124 (typically ground). NMOS transistor T1 is formed by n-well 104, n+ diffusion 114 (source), and gate 118. NMOS transistor T2 is formed by n-well 104, n+ diffusion 116 (source), and gate 120. SCR1 consists of parasitic bipolar pnp transistor Q1 and parasitic bipolar npn transistor Q2 which are formed by p-substrate 102, n-well 104 and diffusions 110, and 114. SCR2 consists of parasitic bipolar pnp transistor Q1 and parasitic bipolar npn transistor Q3 which are formed by p-substrate 102, n-well 104 and diffusions 108, and 116. Resistors R1, R3xe2x80x2 and R3xe2x80x3 are equivalent resistors for the intrinsic resistance of the p-substrate 102 material. Resistors R2, and R4 are equivalent resistors for the intrinsic resistance of the n-well 104 material. Another set of NMOS transistors are arranged in a mirror image around n+ diffusion 116.
FIG. 2, the equivalent circuit of FIG. 1, shows typical parasitic silicon controlled rectifiers SCR1 and SCR2, which are comprised of Q1, Q2, R1 and R2, and Q1, Q2, R3xe2x80x2 and R4, respectively. Note that in the figures like parts are identified by like numerals. Connected in parallel between connection 122 and reference potential 124 are shown the NMOS transistors T1 and to T2 which are protected by the action of the SCRs. Note that SCR1 sees a different resistance (R1) than SCR2 (R1+R3xe2x80x2, where R3xe2x80x2 is between Nodes A and B). Therefore SCR2 turns on easier and has to dissipate more current than SCR1. The non-uniform current distribution is very undesirable, because it limits the maximum voltage that the ESD protection device can withstand. The number of NMOS transistors is not limited to the two shown but depends on the current capacity desired and may be more than two as indicated in FIG. 1.
Other related art is described in the following U.S. Patents which propose low voltage lateral SCRs (LVTSCR), modified lateral SCRs (MLSCR), PMOS-trigger lateral SCRs (PTLSCR), NMOS-trigger lateral SCRs (NTLSCR), and modified PTLSCRs and NTLSCRs to control electrostatic discharge:
U.S. Pat. No. 5,959,820 (Ker et al.) describes a cascode low-voltage triggered SCR and ESD protection circuit.
U.S. Pat. No. 5,905,288 (Ker) describes an output ESD protection circuit with high-current-triggered lateral SCR.
U.S. Pat. No. 5,872,379 (Lee) describes a low voltage turn-on SCR for ESD protection.
U.S. Pat. No. 5,754,381 (Ker) provides a modified PTLSCR and NTLSCR, and bypass diodes for protection of the supply voltage and output pad of an output buffer.
The trigger voltage is the low snap-back trigger voltage of a short-channel PMOS (NMOS) device.
U.S. Pat. No. 5,754,380 (Ker et al.) is similar to U.S. Pat. No. 5,754,381 above but without bypass diodes. The invention requires a smaller layout area than conventional CMOS output buffers with ESD protection.
U.S. Pat. No. 5,745,323 (English et al.) shows several embodiments for protecting semiconductor switching devices by providing a PMOS transistor which turns on when an electrostatic discharge occurs at the output of the circuit.
U.S. Pat. No. 5,576,557 (Ker et al.) provides ESD protection for sub-micron CMOS devices supplying discharge paths at Vdd and Vss using two LVTSCRs. In addition a PMOS device is used in conjunction with one LVTSCR and an NMOS device with the other LVTSCR. Inclusion of the PMOS and NMOS devices allows lowering of the trigger voltage to 11-13 Volt.
U.S. Pat. No. 5,572,394 (Ker et al.) describes a CMOS on-chip four-LVTSCR ESD protection scheme for use in Deep submicron CMOS integrated circuits.
U.S. Pat. No. 5,455,436 (Cheng) describes an SCR ESD protection circuit with a non-LDD NMOS structure with a lower avalanche breakdown level than the LDD NMOS device of an output buffer.
It should be noted that none of the above-cited examples of the related art provide a symmetrical layout of components of the ESD device with a resultant uniform distribution of currents in the parasitic SCRs and thus achieving a combination of high Human Body Model (HBM) ESD Passing Voltage equal to the machine limit of 8 kVolt and a Machine Model voltage of 800V/850Volt.
It is an object of the present invention to provide an ESD device for protecting NMOS high power transistors where the SCR protection device and the NMOS transistors are integrated.
Another object of the present invention is to provide uniform current distribution in the parasitic SCRs associated with the NMOS transistors to provide increased ESD protection limits for the NMOS circuits.
A further object of the present invention is to provide HBM ESD Passing Voltage which equals the machine limit of 8,000 Volt.
A yet further object of the present invention is to provide Machine Model ESD Voltage with a pass/fail range of 800/850 Volt.
These objects have been achieved by designing the ESD device with its two NMOS transistors and its attendant parasitic SCRs in a completely symmetrical arrangement so that the currents are completely uniform in the components which are symmetrical (such as resistors and parasitic bipolar transistor). This symmetry is achieved specifically by adding a p+ diffusion to the source of one of the NMOS transistors. The added p+ diffusion insures that the resistance seen by both SCRs is the same, thus insuring that the current through both SCRs is identical, thereby creating identical turn-on conditions for both SCRs.